1. Field of the Invention
The present invention generally relates to a display device and method for driving the same, and more particularly to a liquid crystal display device and a method for driving the same which are capable of solving a problem of a reduced turn-on current due to a reduced temperature.
2. Description of Prior Art
A liquid crystal display device comprises a plurality of gate lines, a plurality of source lines, and a plurality of pixels. The pixels are aligned as an array. Each one of the pixels is coupled to and controlled by one of the gate lines and one of the source lines for displaying images. Several additional gate driver integrated circuits (IC) provide required driving signals for the gate lines. A gate-in-panel (GIP) type of liquid crystal display (GIP LCD) device is developed recently. The additional gate driver integrated circuits are not used in the GIP LCD device. Driving circuits which are equivalent to the additional gate driver integrated circuits are manufactured on a liquid crystal panel of the GIP LCD device. Since the driving circuits being manufactured on the display panel are substituted for the gate driver integrated circuits, the cost of the gate driver integrated circuits can be reduced. In addition, the driving circuits can be manufactured in the processes of manufacturing the gate lines, the source lines, and the pixels without extra manufacturing processes.
Each of the driving circuits utilized in the GIP LCD device comprises a plurality of shift register units in series. Please refer to FIG. 1, which is a circuit diagram showing a shift register unit 540 and a clock generator 56 in the prior art. The shift register unit 540 comprises an SR flip-flop 5400, a pull-up thin film transistor (TFT) T3, and a pull-down thin film transistor T4. Please refer to FIG. 2, which illustrates a waveform of an output CLK from the clock generator 56. When the pull-up thin film transistor T3 is turned on, a gate line output GNO is the output CLK of the clock generator 56. The signal CLK is a pulse wave having a high level of a first voltage VGH and a low level of a second voltage VEEG. When the signal CLK from the clock generator 56 is at the first voltage VGH and an output from a Q terminal of the SR flip-flop 5400 is at a high level, the pull-up thin film transistor T3 is turned on and the pull-down thin film transistor T4 is turned off. When an output from a Q terminal of the SR flip-flop 5400 is at a high level, the pull-up thin film transistor T3 is turned off and the pull-down thin film transistor T4 is turned on. The gate line output GNO is at a third voltage VGL (not shown).
Please refer to FIG. 3, which illustrates curves indicating relationships between a turn-on current IDS v. a gate voltage VGS (I-V) of the pull-up thin film transistor T3 at different temperatures. As can be seen from FIG. 3, when the gate voltage of the pull-up thin film transistor T3 is fixed and the temperature is reduced, the turn-on current IDS of the pull-up thin film transistor T3 is reduced. The reduced turn-on current IDS will cause a turn-on delay of the gate line output GNO or an insufficient charging time of the pixels which are electrically coupled to the gate line output GNO.
Therefore, there is a need for a solution to the above-mentioned problem of the reduced turn-on current IDS due to the reduced temperature.